Low trigger voltage, low leakage ESD NFET

ABSTRACT

A field effect transistor with associated parasitic lateral npn bipolar junction transistor includes a source region in a substrate, a channel region in the substrate laterally adjacent to the source region, a drain region in the substrate laterally adjacent to the channel region, and a gate above the channel region of the substrate. In addition, a reduced trigger voltage region of the substrate is positioned below the drain region. The reduced trigger voltage region has a threshold voltage of about zero and comprises an undoped region of the pure wafer substrate. Thus, the reduced trigger voltage region is free of implanted N-type and P-type doping.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention generally relates to enhancing the parasitic bipolarturn-on which is formed via the junctions of the field effecttransistor. This includes a reduced trigger/turn-on voltage region (P+zener-like implant beneath the junction) below the drain region thatcomprises an undoped region of the pure wafer substrate.

2. Description of the Related Art

Electrostatic charges are a constant threat to modern electronics.Therefore, electrostatic discharge protection (ESD) devices are animportant component of the protection circuitry provided in today'selectronic devices. As the technologies scale and the ESD protectionrequirements stay constant, effective ESD protection will become evenmore difficult in the future. This drives the need for continuousimprovement and innovation in this area. To be as effective as possible,low trigger voltage ESD protection devices such as N-type field effecttransistors (NFETs) are used because such devices provide effectiveprotection (the parasitic lateral NPN beneath NFET turns on during anESD event), decrease the area of the chip consumed, and reduce thecapacitive loading of the ESD devices. An improved parasitic NPNtransistor that has a low trigger voltage and low leakage and can beeffectively used as an ESD protection device is presented below.

SUMMARY OF THE INVENTION

Disclosed herein is a bipolar junction transistor formed beneath astandard NFET device that includes a source region in a substrate, achannel region in the substrate laterally adjacent to the source region,a drain region in the substrate laterally adjacent to the channel regionand a gate above the channel region of the substrate. The source and thedrain regions have non-silicided upper surfaces. In addition, a P+ zenerlike implant is positioned below the drain region to reduce the triggervoltage of the bipolar junction transistor inherent to the standard NFETdevice. The trigger voltage of a single thick oxide NFET with the P+zener like implant is approximately 5–6V compared to the typical triggervoltage of approximately 7–8V and 8–10V for a stacked or cascaded NFET.In addition, an undoped region of the same resisitivity as the startingwafer is positioned beneath the P+ zener implant to minimize the leakage

A heavily doped P+ implant is positioned in the substrate between theN-type drain region and the substrate. Beneath the P+implant region, theP-well implants have been blocked to minimize leakage (referred to as azero-vt region, with only the starting wafer doping). The compensatingimplant has an opposite doping type of that of the source and drainregion (In the NFET case, a P+ implant is used beneath the N+ drainjunction, but opposite polarities, apply for PFETs). The structure alsoincludes a substrate contact region in the substrate laterally adjacentthe source region. This substrate contact region also has an oppositedoping type to that of the source region. In another embodiment, theP-well implant beneath the substrate is blocked to enable a zero-vtregion. This high resisitivity zero-vt region also helps decrease thetrigger voltage of the npn bipolar junction transistor.

The reduced trigger voltage implant beneath the drain junction lowersthe drain/substrate breakdown voltage of the ESD transistor. Thisenables a smaller drain silicide-blocked region to be used, which lowersthe overall area consumed by the ESD transistor and correspondinglylowers associated capacitance. The zero-vt region beneath the substratecontact increases the substrate resistance which further helps totrigger the npn bipolar transistor at a lower lateral voltage.

These and other aspects of embodiments of the invention will be betterappreciated and understood when considered in conjunction with thefollowing description and the accompanying drawings. It should beunderstood, however, that the following description, while indicatingembodiments of the invention and numerous specific details thereof, isgiven by way of illustration and not of limitation. Many changes andmodifications may be made within the scope of the embodiments of theinvention without departing from the spirit thereof, and the inventionincludes all such modifications.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the invention will be better understood from thefollowing detailed description with reference to the drawings, in which:

FIG. 1 is a cross-section of a non-silicided NFET with the parasitic NPNtransistor shown;

FIG. 2 is a graph showing the i–v characteristics of thesilicide-blocked ESD NFET characteristics of the structure shown in FIG.1;

FIG. 3 is a schematic diagram of a circuit illustrating an NMOS-basednon-self ESD strategy;

FIG. 4 is a schematic diagram of a circuit illustrating an NMOS-basedself-protecting ESD strategy;

FIG. 5 is a cross-section diagram of a transistor with the P+ zener likeimplant;

FIG. 6 is a cross-section diagram of a transistor with the P+ zener likeimplant shown along with the zero-Vt region under the drain junction;and

FIG. 7 is a cross-section schematic diagram of a transistor with the P+zener like implant shown along with the zero-Vt region under the drainand substrate contact regions.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

The embodiments of the invention and the various features andadvantageous details thereof are explained more fully with reference tothe non-limiting embodiments that are illustrated in the accompanyingdrawings and detailed in the following description. It should be notedthat the features illustrated in the drawings are not necessarily drawnto scale. Descriptions of well-known components and processingtechniques are omitted so as to not unnecessarily obscure theembodiments of the invention. For example, the following describes fieldeffect transistors (FETs) and other similar transistor devices (bipolartransistors, etc.). The processes and materials used to create theconductors, impurity regions, insulators, etc. that are used in suchcircuits are well-known to those ordinarily skilled in the art (see forexample U.S. Pat. Nos. 6,720,637 and 6,717,220, which are incorporatedherein by reference) and do not represent points of novelty of theinvention. Therefore, a detailed discussion regarding the processingsteps and materials used to create the following structure isintentionally omitted here from in order to focus the reader upon thesalient features of the invention, and to avoid obscuring the invention.The examples used herein are intended merely to facilitate anunderstanding of ways in which the embodiments of the invention may bepracticed and to further enable those of skill in the art to practicethe embodiments of the invention. Accordingly, the examples should notbe construed as limiting the scope of the invention.

Referring now to the drawings, and more particularly to FIGS. 1 through7, there are shown embodiments of the invention. FIG. 1 illustrates thecross-section of a silicide-blocked ESD (electrostatic discharge) NFET(N-type field effect transistor). More specifically, FIG. 1 illustratesan NFET with an associated parasitic Bipolar Junction Transistor (BJT)100 comprising a substrate 102, a drain region 104 in the substrate 102,a channel region 106 in the substrate 102 laterally adjacent to thedrain region 104, a source region 108 in the substrate 102 laterallyadjacent to the channel region 106, a gate 110 above the channel region106 of the substrate 102, and a substrate contact region 112 in thesubstrate 102 laterally adjacent to the source region 108. The substratecontact region 112 has an opposite doping type (e.g., P-type) of that ofsaid source region 108 (e.g., N-type). The channel region 106 has theopposite type doping of the source 108 and drain regions 104. Therefore,if the source 108 and drain 104 are doped with N-type dopants, thechannel region 106 will be doped with P-type dopants. An isolationregion 122 separates the source region 108 from the substrate contactregion 112.

During a positive mode ESD-event, the junction between the N+drain 104and substrate 102 (drain N+/substrate junction) breaks down and resultsin an avalanche generation of electrons and holes. The holes collectedby the substrate 102 raise the substrate potential to near a diodeturn-on voltage (For example, approximately 0.7V (Vsub=Isub*Rsub)),forward biasing the junction between the source 108 to substrate 102junction and turning on the source (n)-substrate (p)-drain (n) npn BIT.Thus, the source 108, the substrate 102, and the drain 104 make up thenpn region of the BJT. Silicide-blocked regions 114 and 116 (such aspatterned nitride, etc.) near the source 108 and drain 104 provideballasting resistance to ensure uniform current flow. The substratecontact 112 provides sufficient bias to the substrate 102 to ensureproper operation of the BIT.

The characteristics of the above silicide-blocked ESD NFET structure areshown in the graph in FIG. 2. More specifically, as shown in FIG. 2, alower breakdown voltage of N+drain/substrate junction (104/106 junction)and/or a larger substrate 102 resistance (Rsub) is necessary to lowerthe trigger voltage (Vt1) of the lateral npn BIT 100. A smaller drainsilicide-blocked region 114 is desirable to decrease the area ofESD-NFET 100 and the capacitance of ESD device 100.

FIG. 3 illustrates an NMOS/Lnpn (N-type Metal OxideSemiconductor/Lateral npn BJT)-based non-self protecting ESD strategyusing the device 100. More specifically, item 30 represents an inputcircuit and item 32 represents the output driver circuits. Item 34 isthe Charge Device Model (CDM) protection circuit and item 100 is the ESDNFET, as shown in the other figures presented herein. Item 36 representsthe input/output pad. During a positive mode ESD event, the ESDNFET/Lnpn 100 triggers and discharges current to ground. During anegative mode ESD event, the N+/substrate diode (104/106) of the ESDNFET 100 discharges the current to ground. The trigger voltage of theESD device 100 should be lower than the gate oxide breakdown voltage ofthe gates in the receiver circuit 30, and lower than the snapbackvoltage of output driver 32 for all ESD events-CDM, MM (Machine Model)and HBM (Human Body Model) for effective protection.

FIG. 4 illustrates an NMOS-based self-protecting ESD Strategy using thedevice 100 as item 44. This is similar to the structure illustrated inFIG. 3; however, the HBM protection circuit 44 is included within theoutput driver 42. More specifically, in this self-protecting strategy,the output driver 42 also functions as an ESD device. In mixed voltageapplications, the output driver 42 is typically a stacked NFET as shownin FIG. 3. For example, for 3.3V applications, the driver 42 might betwo series 2.5V NFETs as shown in FIG. 3. Also, the trigger voltage ofthe ESD device 100 shown in FIG. 3 should be lower than the breakdownvoltage of the receiver gate 40 and the output driver 32 for all modesof ESD events-HBM, MM and CDM.

For mixed voltage I/O applications, one example of a scenario thatrequires a lower trigger voltage ESD device could include abidirectional 3.3V I/O (e.g., having a driver 32, 42 and receiver 30)that uses a self-protected ESD strategy using a silicide-blocked 2.5VESD NFET similar to the one shown in FIG. 1. If the snapback voltage ofthe stacked NFET 32, 42, is 11V and the breakdown voltage of thereceiver gate 30 is approximately 10–11V, the stacked device 32, 42 willnot be able to protect the 2.5V gate 30 during an HBM event. Further, astacked 2.5V ESD NFET can require a minimum of 4 um silicide-blocking114 on the drain side, which is relatively large, and which carries veryhigh capacitance and area costs.

One solution to this problem is to lower trigger voltage of ESD NFET bylowering breakdown voltage of N+ drain to substrate junction by adding acompensating implant 500 below the drain region 104 that has an oppositedoping type of that of the drain region 104, as shown in FIG. 5. Morespecifically, this p-type region 500 is implanted beneath the drainjunction 104 to lower drain 104/channel 106 (N+/substrate) junctionbreakdown voltage and thereby enable the use of a smaller drain region,which reduces the area consumed by the silicide 114 and similarlyreduces capacitance.

The (P+ zener like) compensating implant 500 can result in high leakagecurrent due to implant damage from deep well implants. Therefore, asshown in FIG. 6, the P-well implant is blocked beneath the implant 500resulting in what is referred to as a zero-Vt region 600. The zero-Vtregion formed beneath the drain junction 104 and compensating implant500 prevents defect formation and results in the reduction of theleakage current. The reduced threshold voltage region 600 lowers N+drain 104/substrate 102 breakdown voltage of the ESD NFET 100 to enablea smaller drain silicide-blocked region 114 to be used and therefore,smaller NFET area and associated capacitance. The zero-Vt region alsoincreases substrate resistance to lower lateral n-p-n trigger voltage ofESD-NFET. Also, as shown in FIG. 7, the zero-Vt region 700 can beintroduced beneath the substrate contact 112 which increases thesubstrate resistance and further lowers the parasitic Lnpn triggervoltage. Both reduced zero-Vt regions 600, 700 have a high sheetresistance (e.g., higher than channel region 106) for a lightly dopednon-epi wafers. Since there are no well implants in this region, onlythe starting wafer doping determines the sheet resistance in theseregions.

Thus, as shown in FIGS. 6 and 7, embodiments herein include a bipolarjunction transistor with an associated parasitic bipolar junctiontransistor. While an NFET type ESD is illustrated in the Figures, oneordinarily skilled in the art would understand that opposite polaritydopants could be used with the invention depending upon the specifics ofthe design. Therefore, for example, a P-type field effect transistor(PFET) embodiment of the invention could utilize the same principlesdiscussed herein and the invention is intended to encompass all suchstructures. The various masking, impurity implanting, patterning, andother similar processing steps used to form the structures in FIGS. 6and 7 would be well-known to those ordinarily skilled in the given thisdisclosure. For example, U.S. Pat. No. 5,504,362 and U.S. PatentPublication 2003/0080382 (incorporated herein by reference) illustratemany processing steps used to form bipolar ESD transistors. While noneof the references incorporated herein disclose the inventive structure,they demonstrate that one ordinarily skilled in the art would readilyunderstand how to make and use the inventive structure disclosed herein.During manufacturing, masking and other well-known processing steps areutilized to prevent the reduced threshold regions 600, 700 fromreceiving any form of doping, such that these regions will remainessentially unaltered regions of the original wafer from which thesubstrate 102 was developed.

As shown in FIGS. 6 and 7, the source region 108 is in the substrate,the channel region 106 is in the substrate laterally adjacent to thesource region 108, the drain region 104 is in the substrate laterallyadjacent to the channel region 106, a gate conductor 110 is above thechannel region 106 of the substrate, and a gate oxide 118 is between thechannel region 106 and the gate 110. The source region 108 and the drainregion 104 can have non-silicided upper surfaces 114, 116. The zero-vtregion 600 of the substrate is positioned below the drain region 104.The zero-vt region 600 comprises an undoped region of the pure wafersubstrate 102. Thus, the zero-Vt region 600 is free of implanted N-typeand P-type doping (starting wafer dopant only in these regions).

The compensating implant 500 and the zero-vt region 600 are positionedin the substrate 102 under the drain region 104 and far enough away fromthe channel region so as not to affect the NFET's threshold voltage. Thecompensating implant 500 has an opposite doping type of that of thesource 108 and drain region 104. The structure also includes a substratecontact region 112 in the substrate 102 laterally adjacent to the sourceregion 108. This substrate contact region 112 also has an oppositedoping type of that of the source region 108. A second zero-vt region700 of the substrate is below the substrate contact region 112. Thesecond zero-Vt region 700 comprises an undoped region of the pure wafersubstrate 102. Thus, the second zero-vt region is also free of N-typeand P-type implanted doping (starting wafer dopant only in theseregions).

Thus, as shown above, the P+ zener implant 500 and the zero-vt regions600, 700 lower the drain 104/substrate 102 breakdown voltage andincrease the substrate resistance to lower the trigger voltage of theESD transistor 100. This enables a smaller drain silicide-blocked region114 to be used, which lowers the overall area consumed by the ESDtransistor and correspondingly lowers associated capacitance.

The foregoing description of the specific embodiments will so fullyreveal the general nature of the invention that others can, by applyingcurrent knowledge, readily modify and/or adapt for various applicationssuch specific embodiments without departing from the generic concept.Therefore, such adaptations and modifications should and are intended tobe comprehended within the meaning and range of equivalents of thedisclosed embodiments. It is to be understood that the phraseology orterminology employed herein is for the purpose of description and not oflimitation. Therefore, while the invention has been described in termsof preferred embodiments, those skilled in the art will recognize thatthe invention can be practiced with modification within the spirit andscope of the appended claims.

1. A transistor device comprising a parasitic bipolar junction deviceunder a field effect transistor, said transistor device comprising: asubstrate; a source region in said substrate, a channel region in saidsubstrate laterally adjacent said source region; a drain region in saidsubstrate laterally adjacent said channel region; a gate above saidchannel region of said substrate; and a reduced threshold voltage regionof said substrate only below said drain region, wherein said reducedthreshold voltage region has a lower threshold voltage than saidsubstrate.
 2. The transistor device in claim 1, further comprising acompensating implant in said substrate between said drain region andsaid reduced threshold voltage region.
 3. The transistor device in claim2, wherein said compensating implant has an opposite doping type of thatof said drain region.
 4. The transistor device in claim 1, furthercomprising a substrate contact region in said substrate laterallyadjacent to said source region, wherein said substrate contact regionhas an opposite doping type of that of said source region.
 5. Thetransistor device in claim 4, further comprising a secondary reducedthreshold voltage region of said substrate below said substrate contactregion.
 6. The transistor device in claim 1, wherein, said source regionand said drain region have non-silicided upper surfaces.
 7. Thetransistor device in claim 1, wherein, said reduced threshold voltageregion is free of impurities in said channel region.
 8. A bipolarjunction N-type field effect transistor comprising: a substrate; aN-type source region in said substrate, a P-type channel region in saidsubstrate laterally adjacent to said source region; a N-type drainregion in said substrate laterally adjacent to said channel region; agate above said channel region of said substrate; and a reducedthreshold voltage region of said substrate only below said drain regionthat is free of N-type and P-type doping.
 9. The transistor in claim 8,further comprising a compensating implant in said substrate between saiddrain region and said reduced threshold voltage region.
 10. Thetransistor in claim 9, wherein said compensating implant has P-typedoping.
 11. The transistor in claim 8, further comprising a substratecontact region in said substrate laterally adjacent to said sourceregion, wherein said bias region has P-type doping.
 12. The transistorin claim 11, further comprising a secondary reduced threshold voltageregion of said substrate below said substrate contact region.
 13. Thetransistor in claim 8, wherein, said source region and said drain regionhave silicided upper surfaces.
 14. The transistor in claim 8, wherein,said reduced threshold voltage region comprises an undoped wafermaterial.
 15. A bipolar junction transistor comprising: a pure wafersubstrate; a source region in said substrate, a channel region in saidsubstrate laterally adjacent to said source region; a drain region insaid substrate laterally adjacent to said channel region; a gate abovesaid channel region of said substrate; and a reduced threshold voltageregion of said substrate only below said drain region that comprises anundoped region of said pure wafer substrate.
 16. The transistor in claim15, further comprising a compensating implant in said substrate betweensaid drain region and said reduced threshold voltage region.
 17. Thetransistor in claim 16, wherein said compensating implant has anopposite doping type of that of said drain region.
 18. The transistor inclaim 15, further comprising a substrate contact region in saidsubstrate laterally adjacent to said source region, wherein said biasregion has an opposite doping type of that of said source region. 19.The transistor in claim 18, further comprising a secondary reducedthreshold voltage region of said substrate below said substrate contactregion.
 20. The transistor in claim 15, wherein, said source region andsaid drain region have silicided upper surfaces.